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CY2545 CY2547
Quad PLL Programmable Spread Spectrum Clock Generator with Serial I2C Interface
Features

Glitch-free outputs while frequency switching 24-pin QFN package Commercial and industrial temperature ranges
Four fully integrated phase locked loops (PLLs) Input frequency range External crystal: 8 to 48 MHz External reference: 8 to 166 MHz clock Wide operating output frequency range 3 to 166 MHz Serial programmable over 2-wire I2C interface Programmable spread spectrum with center and down spread option and Lexmark and Linear modulation profiles VDD supply voltage options: 2.5V, 3.0V, and 3.3V for CY2545 1.8V for CY2547 Selectable output clock voltages independent of VDD supply: 2.5V, 3.0V, and 3.3V for CY2545 1.8V for CY2547 Power down, output enable, or frequency select features Low jitter, high accuracy outputs Ability to synthesize nonstandard frequencies with Fractional-N capability Up to eight clock outputs with programmable drive strength
Benefits

Multiple high performance PLLs allow synthesis of unrelated frequencies Nonvolatile programming for personalization of PLL frequencies, spread spectrum characteristics, drive strength, crystal load capacitance, and output frequencies Application specific programmable EMI reduction using Spread Spectrum for clocks Programmable PLLs for system frequency margin tests Meets critical timing requirements in complex system designs Suitability for PC, consumer, portable, and networking applications Capable of Zero PPM frequency synthesis error Uninterrupted system operation during clock frequency switch Application compatibility in standard and low power systems

Logic Block Diagram
CLKIN/RST Crossbar XIN/ EXCLKIN XOUT OSC PLL1
Dividers and Drive Bank 2
CLK1
Output Bank 1
Switch
CLK2
CLK3 CLK4 CLK5 CLK6
Bank 3
PLL2 MUX and Control Logic
Strength Control
FS
CLK7 CLK8
PLL3 (SS)
SCL SDA SSON I2C PLL4 (SS) PD#/OE
Cypress Semiconductor Corporation Document #: 001-13196 Rev. *A
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised October 05, 2007
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CY2545 CY2547
Pinouts
Figure 1. Pin Diagram - CY2545 24 LD QFN
CLKIN/RST
XIN/ EXCLKIN
XOUT
CLK8
20
24
23
22
21
GND CLK1 VDD_CLK_B1 PD#OE
1
GND
19 18
VDD
GND CLK7 VDD_CLK_B3
2
17
3
CY2545 24LD QFN
16
4
15
CLK6/SSON VDD_CLK_B2
DNU CLK2
5
14
6
13
CLK5
7
8
9
10
11
12
CLK4
SCL
SDA
Table 1. Pin Definition - CY2545 24 LD QFN (VDD = 2.5V, 3.0V or 3.3V Supply) Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND CLK1 VDD_CLK_B1 PD#/OE DNU CLK2 GND SCL SDA CLK3/FS CLK4 GND CLK5 VDD_CLK_B2 CLK6/SSON Name Power Output Power Input DNU Output Power Input Input/Output Output/Input Output Power Output Power Output/Input IO Power supply ground Programmable clock output. Output voltage depends on Bank1 voltage Power supply for Bank1 (CLK1, CLK2) output: 2.5V/3.0V/3.3V Multifunction programmable pin: Output enable or Power down mode Do not use this pin Programmable clock output. Output voltage depends on Bank1 voltage Power supply ground Serial data clock Serial data input/output Multifunction programmable pin: Programmable clock output or frequency select input pin. Output voltage of CLK3 depends on Bank2 voltage Programmable clock output. Output voltage depends on Bank2 voltage Power supply ground Programmable clock output. Output voltage depends on Bank2 voltage Power supply for Bank2 (CLK3, CLK4, CLK5) output: 2.5V/3.0V/3.3V Multifunction programmable pin: Programmable clock output or spread spectrum ON/OFF control input pin. Output voltage of CLK6 depends on Bank3 voltage Power supply for Bank3 (CLK6, CLK7, CLK8) output: 2.5V/3.0V/3.3V Programmable clock output. Output voltage depends on Bank3 voltage Power supply ground Power supply ground Programmable clock output. Output voltage depends on Bank3 voltage Multifunction programmable pin. High true reset input or 2.5V/3.0V/3.3V external reference clock input. The signal level of CLKIN input must track VDD power supply on pin 22. Description
16 17 18 19 20 21
VDD_CLK_B3 CLK7 GND GND CLK8 CLKIN/RST
Power Output Power Power Output Input/Input
Document #: 001-13196 Rev. *A
CLK3/FS
GND
GND
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Table 1. Pin Definition - CY2545 24 LD QFN (VDD = 2.5V, 3.0V or 3.3V Supply) (continued) Pin Number 22 23 24 VDD XOUT XIN/EXCLKIN Name Power Output Input IO Crystal output Crystal input or 1.8V external clock input Figure 2. Pin Diagram - CY2547 24 LD QFN
XIN/ EXCLKIN
Description Power supply for core and inputs: 2.5V/3.0V/3.3V
XOUT
CLKIN/RST
CLK8
20
24
23
22
21
GND CLK1 VDD_CLK_B1 PD#OE
1
GND
19 18
VDD
GND CLK7 VDD_CLK_B3
2
17
3
CY2547 24LD QFN
16
4
15
CLK6/SSON VDD_CLK_B2
VDD CLK2
5
14
6
13
CLK5
7
8
9
10
11
12
CLK4
SCL
Table 2. Pin Definition - CY2547 24 LD QFN (VDD = 1.8V Supply) Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND CLK1 VDD_CLK_B1 PD#/OE VDD CLK2 GND SCL SDA CLK3/FS CLK4 GND CLK5 VDD_CLK_B2 CLK6/SSON Name Power Output Power Input Power Output Power Input Input/Output Output/Input Output Power Output Power Output/Input IO Power supply ground Programmable clock output. Output voltage depends on Bank1 voltage Power supply for Bank1 (CLK1, CLK2) output: 1.8V Multifunction programmable pin: Output enable or Power down mode Power supply for core and inputs: 1.8V Programmable output clock. Output voltage depends on Bank1 voltage Power supply ground Serial data clock Serial data input Multifunction programmable pin: Programmable clock output or frequency select input pin. Output voltage of CLK3 depends on VDD_CLK_B2 voltage Programmable output clock. Output voltage depends on Bank2 voltage Power supply ground Programmable clock output. Output voltage depends on Bank2 voltage Power supply for Bank2 (CLK3, CLK4, CLK5) output: 1.8V Multifunction programmable pin: Programmable clock output or spread spectrum ON/OFF control input pin. Output voltage of CLK6 depends on VDD_CLK_B3 voltage Power supply for Bank3 (CLK6, CLK7, CLK8) output: 1.8V Programmable clock output. Output voltage depends on Bank3 voltage Power supply ground Description
16 17 18
VDD_CLK_B3 CLK7 GND
Power Output Power
Document #: 001-13196 Rev. *A
CLK3/FS
SDA
GND
GND
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Table 2. Pin Definition - CY2547 24 LD QFN (VDD = 1.8V Supply) (continued) Pin Number 19 20 21 22 23 24 GND CLK8 CLKIN/RST VDD XOUT XIN/EXCLKIN Name Power Output Input/Input Power Output Input IO Power supply ground Programmable clock output. Output voltage depends on Bank3 voltage Multifunction programmable pin: High true reset input or 1.8V external low voltage reference clock input Power supply for core and inputs: 1.8V Crystal output Crystal input or 1.8V external clock input Description
General Description
Four Configurable PLLs
The CY2545 and CY2547 have four I C programmable PLLs available to generate output frequencies ranging from 3 to 166 MHz. The advantage of having four PLLs is that a single device generates up to four independent frequencies from a single crystal. Two sets of frequencies for each PLL can be programmed. This enables in system frequency switching using multifunction frequency select pin, FS.
2
Output Source Selection
These devices have eight clock outputs (CLK1 - 8). There are six available clock sources for these outputs. These clock sources are: XIN/EXCLKIN, CLKIN, PLL1, PLL2, PLL3, or PLL4. Output clock source selection is done using four out of six crossbar switch. Thus, any one of these six available clock sources can be arbitrarily selected for the clock outputs. This gives user a flexibility to have up to four independent clock outputs.
I2C Programming
The CY2545 and CY2547 have a serial interface that programs the configuration memory array to synthesize output frequencies by programmable output divider, spread characteristics, drive strength, and crystal load capacitance. I2C can also be used for in system control of these programmable features. I 2C
Spread Spectrum Control
Two of the four PLLs (PLL3 and PLL4) have spread spectrum capability for EMI reduction in the system. The device uses a Cypress proprietary PLL and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the PLL. The spread spectrum feature can be turned on or off using a multifunction control pin (CLK7/SSON). It can be programmed to either center spread range from 0.125% to 2.50% or down spread range from -0.25% to -5.0% with Lexmark or Linear profile.
Input Reference Clocks
The input to the CY2545 and CY2547 is either a crystal or a clock signal. The input frequency range for crystals is 8 MHz to 48 MHz. There is provision for two reference clock inputs, CLKIN and EXCLKIN with frequency range of 8 MHz to 166 MHz. For both devices, when CLKIN signal at pin 21 is used as a reference input, a valid signal at EXCLKIN (as specified in the AC and DC Electrical Specification table), must be present for the devices to operate properly.
Frequency Select
The device can store two different PLL frequency configurations, output source selection and output divider values for all eight outputs in its nonvolatile memory location. There is a multifunction programmable pin, CLK3/FS which, if programmed as frequency select input, can be used to select between these two arbitrarily programmed settings.
Multiple Power Supplies
The CY2545 and CY2547 are designed to operate at internal core supply voltage of 1.8V. In the case of the high voltage part (CY2545), an internal regulator is used to generate 1.8V from the 2.5V/3.0V/3.3V VDD supply voltage at pin 22. For the low voltage part (CY2547), this internal regulator is bypassed and 1.8V at VDD pin 22 is directly used.
Glitch-Free Frequency Switch
When the frequency select pin (FS) is used to switch frequency, the outputs are glitch-free provided frequency is switched using output dividers. This feature enables uninterrupted system operation while clock frequency is switched.
Device Reset Function
There is a multifunction CLKIN/RST (pin 21) that can be programmed to use for the device reset function. There are two different programmable modes of operation for this device reset function. First one (called POR like reset), when used brings the device in the default register settings loosing all configuration changes made through the I2C interface. The second (called Clean Start), keeps the I2C programmed values while giving all outputs a simultaneous clean start from its low pull down state.
Output Bank Settings
These devices have eight clock outputs grouped in three output driver banks. The Bank 1, Bank 2, and Bank 3 correspond to (CLK1, CLK2), (CLK3, CLK4, CLK5), and (CLK6, CLK7, CLK8), respectively. Separate power supplies are used for each of these banks and they can be any of 2.5V, 3.0V, or 3.3V for CY2545 and 1.8V for CY2547 giving user multiple choice of output clock voltage levels.
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PD#/OE Mode
PD#/OE (Pin 4) is programmable to operate as either power down (PD#) or output enable (OE) mode. PD# is a low true input. If activated it shuts off the entire chip, resulting in minimum device power consumption. Setting this signal high brings the device into operational mode with default register settings. When this pin is programmed as output enable (OE), clock outputs are enabled or disabled using OE pin. Individual clock outputs can be programmed to be sensitive to this OE pin.
Output Drive Strength
The DC drive strength of the individual clock output can be programmed for different values. Table 3 shows the typical rise and fall times for different drive strength settings. Table 3. Output Drive Strength Output Drive Strength Low Mid Low Mid High High Rise/Fall Time (ns) (Typical Value) 6.8 3.4 2.0 1.0
Keep Alive Mode
By activating the device in the keep alive mode, power down mode is changed to power saving mode. This disables all PLLs and outputs, but preserves the contents of the volatile registers. Thus, any configuration changes made through the I2C interface are preserved. By deactivating the keep alive mode, I2C memory is not preserved during power down, but power consumption is reduced relative to the keep alive mode.
Generic Configuration and Custom Frequency
There is a generic set of output frequencies available from the factory that can be used for the device evaluation purposes. The device, CY2545/CY2547 can be custom programmed to any desired frequencies and listed features. For customer specific programming and I2C programmable memory bitmap definitions, please contact your local Cypress Field Application Engineer (FAE) or sales representative.
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CY2545 CY2547
Serial I2C Programming Interface Protocol and Timing
To enhance the flexibility and function of the clock synthesizer, a two signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, are individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power up and therefore, use of this interface is optional. Clock device register changes are normally made at system initialization, if any are required. The CY2545 and CY2547 use a 2-wire serial interface SDA and SCL that operates up to 400 kbits/s in read or write mode. The SDA and SCL timing and data transfer sequence is shown in Figure 3. The basic write serial format is: Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in MA+2; ACK; etc. until STOP Bit. The basic serial format is illustrated in Figure 4.
eight bits must contain the data word intended for storage. After the data word is received, the slave responds with another acknowledge bit (ack = 0/LOW), and the master must end the write sequence with a STOP condition.
Writing Multiple Bytes
To write multiple bytes at a time, the master does not end the write sequence with a STOP condition; instead, the master sends multiple contiguous bytes of data to be stored. After each byte, the slave responds with an acknowledge bit, the same as after the first byte, and accepts data until the STOP condition responds to the acknowledge bit. When receiving multiple bytes, the CY2545 and CY2547 internally increment the register address.
Read Operations
Read operations are initiated the same way as write operations except that the R/W bit of the slave address is set to `1' (HIGH). There are three basic read operations: current address read, random read, and sequential read.
Device Address
The device serial interface address is 69H. The device address is combined with a read/write bit as the LSB and is sent after each start bit.
Current Address Read
The CY2545 and CY2547 have an onboard address counter that retains 1 more than the address of the last word access. If the last word written or read was word `n', then a current address read operation returns the value stored in location `n+1'. When the CY2545/CY2547 receive the slave address with the R/W bit set to a `1', the CY2545/CY2547 issue an acknowledge and transmit the 8-bit word. The master device does not acknowledge the transfer, but generates a STOP condition, which causes the CY2545/CY2547 to stop transmission.
Data Valid
Data is valid when the clock is HIGH, and is only transitioned when the clock is LOW, as illustrated in Figure 5.
Data Frame
A start and stop sequence indicates every new data frame, as illustrated in Figure 6. Start Sequence - The start frame is indicated by SDA going LOW when SCL is HIGH. Every time a start signal is supplied, the next 8-bit data must be the device address (seven bits) and a R/W bit, followed by register address (eight bits) and register data (eight bits). Stop Sequence - The stop frame is indicated by SDA going HIGH when SCL is HIGH. A stop frame frees the bus to go to another part on the same bus or to another random register address.
Random Read
Through random read operations, the master may access any memory location. To perform this type of read operation, first the word address must be set. This is done by sending the address to the CY2545/CY2547 as part of a write operation. After sending the word address, the master generates a START condition following the acknowledge. This terminates the write operation before any data is stored in the address, but not before the internal address pointer is set. Next, the master reissues the control byte with the R/W byte set to `1'. The CY2545/CY2547 then issue an acknowledge and transmit the 8-bit word. The master device does not acknowledge the transfer, but generates a STOP condition, which causes the CY2545/CY2547 to stop transmission.
Acknowledge Pulse
During write mode the CY2545/CY2547 responds with an acknowledge pulse after every eight bits. Do this by pulling the SDA line LOW during the N*9th clock cycle as illustrated in Figure 7 (N = the number of bytes transmitted). During read mode, the master generates the acknowledge pulse after reading the data packet.
Sequential Read
Sequential read operations follow the same process as random reads except that the master issues an acknowledge instead of a STOP condition after transmitting the first 8-bit data word. This action increments the internal address pointer, and subsequently output of the next 8-bit data word. By continuing to issue acknowledges instead of STOP conditions, the master serially reads the entire contents of the slave device memory. When the internal address pointer points to the FFH register, after the next increment, the pointer points to the 00H register.
Write Operations
Writing Individual Bytes
A valid write operation must have a full 8-bit register address after the device address word from the master, which is followed by an acknowledge bit from the slave (ack = 0/LOW). The next
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Figure 3. Data Transfer Sequence on the Serial Bus
SCL
SDA
Address or Acknowledge Valid Data may be changed STOP Condition
START Condition
Figure 4. Data Frame Architecture SDA Write Multiple Contiguous Registers
Start Signal 1 Bit Slave ACK 1 Bit 1 Bit Slave R/W = 0 ACK 7-bit Device Address 1 Bit Slave ACK 1 Bit Slave ACK 8-bit Register Data (XXH+1) 1 Bit Slave ACK 8-bit Register Data (XXH+2) 1 Bit Slave ACK 8-bit Register Data (FFH) 1 Bit Slave ACK 1 Bit Slave ACK 1 Bit Slave ACK
8-bit Register Address (XXH)
8-bit Register Data (XXH)
8-bit Register Data (00H) Stop Signal
SDA Read Current Address Read Start Signal
1 Bit 1 Bit Slave R/W = 1 ACK 7-bit Device Address
1 Bit Master ACK
8-bit Register Data Stop Signal
SDA Read Multiple Contiguous Registers
Start Signal
1 Bit 1 Bit Slave ACK R/W = 0 7-bit Device Address
1 Bit Slave ACK
1 Bit Master ACK 8-bit Register Data (XXH)
1 Bit Master ACK 8-bit Register Data (XXH+1)
1 Bit Master ACK 8-bit Register Data (FFH)
1 Bit Master ACK
1 Bit Master ACK
1 Bit Master ACK
8-bit Register Address (XXH)
7-bit Device Address +R/W=1
8-bit Register Data (00H) Stop Signal
Repeated Start bit
Figure 5. Data Valid and Data Transition Periods
Data Valid Transition to next Bit
SDA
tDH
tSU
CLKHIGH VIH
SCL
VIL
CLKLOW
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Serial I2C Programming Interface Timing
Figure 6. .Start and Stop Frame
SDA
START
Transition to next Bit
SCL
STOP
Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data) SDA
+
START DA6 DA5 DA0 R/W ACK RA7
+
RA6 RA1 RA0 ACK D7 D6
+
D1 D0 ACK STOP
SCL
+
+
+
Serial I2C Programming Interface Timing Specifications
Parameter fSCL CLKLOW CLKHIGH tSU tDH Frequency of SCL Start Mode Time from SDA LOW to SCL LOW SCL LOW Period SCL HIGH Period Data Transition to SCL HIGH Data Hold (SCL LOW to data transition) Rise Time of SCL and SDA Fall Time of SCL and SDA Stop Mode Time from SCL HIGH to SDA HIGH Stop Mode to Start Mode Description Min - 0.6 1.3 0.6 250 0 - - 0.6 1.3 Max 400 - - - - - 300 300 - - Unit kHz s s s ns ns ns ns s s
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CY2545 CY2547
Absolute Maximum Conditions
Parameter VDD VDD VDD_CLK_BX VIN VIN TS ESDHBM UL-94 MSL Description Supply voltage for CY2545 Supply Voltage for CY2547 Output Bank supply voltage Input voltage for CY2545 Input voltage for CY2547 Temperature and storage ESD protection (Human Body Model) Flammability rating Moisture sensitivity level Relative to VSS Relative to VSS Nonfunctional JEDEC EIA/JESD22-A114-E V-0 @1/8 in. 3 Condition Min -0.5 -0.5 -0.5 -0.5 -0.5 -65 2000 10 Max 4.5 2.6 4.5 VDD+0.5 2.2 +150 Unit V V V V V C Volts ppm
Recommended Operating Conditions
Parameter VDD VDD VDD_CLK_BX TAC TAI CLOAD tPU Description VDD Operating voltage for CY2545 VDD Operating voltage for CY2547 Output driver voltage for Bank 1, 2 and 3 Commercial ambient temperature Industrial ambient temperature Maximum load capacitance Power up time for all VDD to reach minimum specified voltage (power ramps must be monotonic) Min 2.25 1.65 1.43
0 -40 - 0.05
Typ - 1.8 -
- -- -
Max 3.60 1.95 3.60
+70 +85 15 500
Unit V V V
C C pF ms
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CY2545 CY2547
DC Electrical Specifications
Parameter VOL Description Output low voltage Conditions IOL = 2 mA, drive strength = [00] IOL = 3 mA, drive strength = [01] IOL = 7 mA, drive strength = [10] IOL = 12 mA, drive strength = [11] VOH Output high voltage IOH = -2 mA, drive strength = [00] IOH = -3 mA, drive strength = [01] IOH = -7 mA, drive strength = [10] IOH = -12 mA, drive strength = [11] VOLSD VIL1
VIL2 VIL3 VIL4
Min -
Typ -
Max 0.4
Unit V
VDD_CLK_BX - 0.4
-
-
V
Output low voltage, SDA Input low voltage of PD#/OE, RST, FS, and SSON Input low voltage of CLKIN for CY2545 Input low voltage of EXCLKIN for CY2545 Input low voltage of CLKIN, EXCLKIN for CY2547 Input high voltage of PD#/OE, RST, FS, and SSON Input high voltage of CLKIN for CY2545 Input high voltage of EXCLKIN for CY2545 Input high voltage of CLKIN, EXCLKIN for CY2547 Input low current of RST and PD#/OE Input high current of RST and PD#/OE Input low current of SSON and FS
IOL = 4 mA
- - - - - 0.8*VDD 0.9*VDD 1.62 0.9*VDD
- - - - - - - - - - - - - 160
0.4 0.2*VDD 0.1*VDD 0.18 0.1*VDD - - 2.2 - 10 10 10 36 250
V V V V V V V V V A A A A k
VIH1
VIH2 VIH3 VIH4
IILPD IIHPD IILSR IIHSR RDN IDD[1,2] IDDS
[1]
VIL = 0V VIH = VDD VIL = 0V (Internal pull dn = 160k typ)
- - - 14 100
Input high current of SSON and VIH = VDD (Internal pull dn = 160k typ) FS Pull down resistor of (CLK1-CLK8) when off, CLK6/SSON and CLK3/FS Supply current for CY2547 Supply current for CY2545 Standby current Power down current Input capacitance PD# = High, No load PD# = High, No load PD# = Low, No load, with I C circuit not in Keep Alive Mode PD# = Low, No load, with I2C circuit in Keep Alive Mode SSON, RST, PD#/OE or FS inputs
2
- - - - -
20 22 3 -
- - - 1 7
mA mA A mA pF
IPD[1] CIN[1]
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CY2545 CY2547
AC Electrical Specifications
Parameter FIN (crystal) FIN (clock) FCLK DC1 DC2 TRF1
[1]
Description Crystal frequency, XIN Input clock frequency Output clock frequency Output duty cycle, all clocks except Ref Out Ref out clock duty cycle Output rise/fall time Output rise/fall time Output rise/fall time Output rise/fall time Cycle-to-cycle jitter max (Pk-Pk) PLL Lock time
Conditions Clock inputs CLKIN or EXCLKIN Duty cycle is defined in Figure 9; t1/t2, measured 50% of VDD Ref In Min 45%, Max 55% Measured from 20% to 80% of VDD_CLK_BX, as shown in Figure 10, CLOAD = 15 pF, Drive strength [00] Measured from 20% to 80% of VDD_CLK_BX, as shown in Figure 10, CLOAD = 15 pF, Drive strength [01] Measured from 20% to 80% of VDD_CLK_BX, as shown in Figure 10, CLOAD = 15 pF, Drive strength [10] Measured from 20% to 80% of VDD_CLK_BX, as shown in Figure 10, CLOAD = 15 pF, Drive strength [11] Configuration dependent. See Table 4 Measured from 90% of the applied power supply level
Min
8 8 3 45
Typ - - -
50
Max
48 166 166 55
Unit
MHz MHz MHz %
40 - - - - - -
- 6.8 3.4 2.0 1.0 150 1
60 - - - - - 3
% ns ns ns ns ps ms
TRF2[1] TRF3[1] TRF4[1] TCCJ[1,2] TLOCK
[1]
Table 4. Configuration Example for C-C Jitter Ref. Freq. (MHz) 14.3181 19.2 27 48 CLK1 Output Freq. (MHz) 8.0 74.25 48 48 C-C Jitter Typ (ps) 134 99 67 93 CLK2 Output Freq. (MHz) 166 166 27 27 C-C Jitter Typ (ps) 103 94 109 123 CLK3 Output Freq. (MHz) 48 8 166 166 C-C Jitter Typ (ps) 92 91 103 137 CLK4 Output Freq. (MHz) 74.25 27 74.25 166 C-C Jitter Typ (ps) 81 110 97 138 8 48 CLK5 Output Freq. (MHz) C-C Jitter Typ (ps) 75 Not Used 103
Not Used
Recommended Crystal Specification for SMD Package
Parameter Fmin Fmax R1 C0 CL DL(max) Minimum frequency Maximum frequency Motional resistance (ESR) Shunt capacitance Parallel load capacitance Maximum crystal drive level Description Range 1 8 14 135 4 18 300 Range 2 Range 3 14 28 50 4 14 300 28 48 30 2 12 300 Unit MHz MHz pF pF W
Recommended Crystal Specification for Thru-Hole Package
Parameter Fmin Fmax R1 C0 CL DL(max) Minimum frequency Maximum frequency Motional resistance (ESR) Shunt capacitance Parallel load capacitance Maximum crystal drive level Description Range 1 8 14 90 7 18 1000 Range 2 Range 3 14 24 50 7 12 1000 24 32 30 7 12 1000 Unit MHz MHz pF pF W
Notes 1. Guaranteed by design but not 100% tested. 2. Configuration dependent.
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Test and Measurement Setup
Figure 8. Test and Measurement Setup
V DD 0.1 F DUT Outputs C LOAD
GND
Voltage and Timing Definitions
Figure 9. Duty Cycle Definition
t1 t2 VDD_CLK_BX 50% of V Clock Output 0V
DD_CLK_BX
Figure 10. Rise Time = TRF, Fall Time = TRF
TRF TRF V DD_CLK_BX 80% of V 20% of V 0V
DD_CLK_BX
Clock Output
DD_CLK_BX
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Ordering Information
Part Number[1] Pb-free CY2545Cxxx CY2545CxxxT CY2547Cxxx CY2547CxxxT CY2545Ixxx CY2545IxxxT CY2547Ixxx CY2547IxxxT 24-pin QFN 24-pin QFN 24-pin QFN 24-pin QFN Supply voltage: 2.5V, 3.0V or 3.3V Supply voltage: 1.8V Supply voltage: 2.5V, 3.0V or 3.3V Supply voltage: 1.8V Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C Industrial, -40C to 85C Industrial, -40C to 85C Industrial, -40C to 85C Industrial, -40C to 85C 24-pin QFN Tape & Reel Supply voltage: 2.5V, 3.0V or 3.3V 24-pin QFN Tape & Reel Supply voltage: 1.8V 24-pin QFN Tape & Reel Supply voltage: 2.5V, 3.0V or 3.3V 24-pin QFN Tape & Reel Supply voltage: 1.8V Type VDD(V) Production Flow
Note 1. xxx indicates Factory Programmable and are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative.
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Package Drawing and Dimensions
Figure 11. 24-LD QFN 4x4 mm (Subcon Punch Type Pkg with 2.49x2.49 EPAD) LF24A/LY24A
SIDE VIEW TOP VIEW
0.05 3.90 4.10 ?0.50 N 1 2 2.45 2.55 3.70 3.80 3.90 4.10 2.49
SOLDERABLE EXPOSED PAD
BOTTOM VIEW
C 0.230.05 2.49 0.20 REF. N 1 2 0.45 PIN1 ID 0.20 R. 1.00 MAX. 0.05 MAX. 0.80 MAX.
3.70 3.80
0.30-0.50 0-12 C SEATING PLANE 0.420.18 (4X) 2.45 2.55
0.50
NOTES: 1. HATCH IS SOLDERABLE EXPOSED METAL.
51-85203-*A
2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.042g 4. ALL DIMENSIONS ARE IN MM [MIN/MAX] 5. PACKAGE CODE PART # LF24A LY24A DESCRIPTION STANDARD LEAD FREE
Document #: 001-13196 Rev. *A
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CY2545 CY2547
Document History Page
Document Title: CY2545 CY2547 Quad PLL Programmable Spread Spectrum Clock Generator with Serial I2C Interface Document Number: 001-13196 REV. ** *A ECN NO. 870780 1504843 Issue Date See ECN See ECN Orig. of Change RGL/AESA New Data Sheet RGL/AESA Changed I2C Tsu specification from 100ns to 250 ns Changed ESD spec from MIL-STD to JEDEC Combined VDD operating condition spec for CY2545 to a single VDD spec Changed name from VDD_CORE to VDD Description of Change
(c) Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-13196 Rev. *A
Revised October 05, 2007
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Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders.
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